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wafer.space Community
🏗️ - Designing / cob
Channel for discussing chip-on-board packaging options for wafer.space bare die.
Between 2025-08-31 11:59 p.m. and 2025-10-01 12:00 a.m.
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Tim 'mithro' Ansell 2025-09-08 4:49 p.m.
I just found
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Tim 'mithro' Ansell 2025-09-11 1:13 a.m.
@Tim Edwards - Lots of discussion about padrings and such is happening here.
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I designed and ordered a PCB layout to let me test COB, even though I don't have a wire bonder yet. But I'm increasingly ready to experiment!
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Tim 'mithro' Ansell 2025-09-12 8:33 p.m.
@Tholin - Have you uploaded your PCB layout somewhere?
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Going to wait at least until the board house has reviewed the layout and declared it manufacturable
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Alright, no complaints so far and its mid-production. Hold on.
4:47 p.m.
4:47 p.m.
Here's a preview
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Tim 'mithro' Ansell 2025-09-13 5:56 p.m.
@Tholin - Where are you getting it manufactured?
6:22 p.m.
I selected ENIG so all the pads are gold-plated. Hopefully that will be enough.
6:22 p.m.
Its not actually too terribly expensive.
6:25 p.m.
JLC quotes $120 for 100 4-layer PCBs up to 100mm by 100mm with ENIG, which comes down to just $1.20 per board.
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But where do you get them wire bonded ?
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Tim 'mithro' Ansell 2025-09-13 6:34 p.m.
FWIW - I finally got a contact at JLCPCB, will see if I can get to someone who can help with getting wire bonding offered.
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I am trying to obtain a wire bonder of my own
6:52 p.m.
Experimenting with Chip On Board setups for GF180MCU chips, most importantly gf180 Caravel. - AvalonSemiconductors/gf180mcu_cob
6:57 p.m.
Based on the RISC-V core on my multi-project die
6:57 p.m.
Outside of the COB, the rest of the PCB is as simple and bodge-able as possible.
6:57 p.m.
Just in case
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Have you ever tried working with a wire bonder?
7:42 p.m.
@stuart and Matt did in the past, and it was... pretty challenging
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Well, practice makes perfect, right?
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can confirm they are pretty hateful machines 😅
12:32 a.m.
fun while working, very frustrating when not
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Tim 'mithro' Ansell 2025-09-19 7:03 p.m.
7:03 p.m.
@Andrew Wingate was playing with some castellated edge boards.
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Nice! One power domain?
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What's the pitch on those ? 1.27 mm ? or 1 mm ?
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Tim 'mithro' Ansell 2025-09-19 7:23 p.m.
I think 1mm but have to wait for what @Andrew Wingate says
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Andrew Wingate 2025-09-19 7:43 p.m.
Yes, the pitch is 1mm as shown. I hadn't realized how large the ring for the bonding wires was so there's a lot more room than I had thought. All this is a bit of an exploration into what's the best form factor for:
  • ease of use
  • easiest for the wire bonders themselves
  • if you want many of them I am open to suggestions.
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tbh that COB footprint I made could be scaled down. The power/ground rings can be closer to the die, I think.
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Tholin
tbh that COB footprint I made could be scaled down. The power/ground rings can be closer to the die, I think.
Andrew Wingate 2025-09-19 7:59 p.m.
Sounds great. Thank you for the baseline. I am just playing around a bit.
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@Andrew Wingate Also see https://discord.com/channels/1361349522684510449/1418540236148838461 thread which has the pad frame and how it should be bonded out.
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Andrew Wingate 2025-09-19 8:00 p.m.
This whole panel is 100mm on a side. and from what I've seen should fit in the wire bonding machines I've seen.
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@Tim 'mithro' Ansell What's the die thickness ? Are they going through thinning ?
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tnt
@Andrew Wingate Also see https://discord.com/channels/1361349522684510449/1418540236148838461 thread which has the pad frame and how it should be bonded out.
Andrew Wingate 2025-09-19 8:05 p.m.
I am seeing 64 pins? Is that what we should be shooting for. I was under the assumption there were no hard standards and was shooting for something that could cover most use cases while being easy for people to work with. There were also some suggestions for this same kind of thing but with .1" spacing and the ability to breadboard. Is there interest in that variation as well?
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tnt
@Tim 'mithro' Ansell What's the die thickness ? Are they going through thinning ?
Tim 'mithro' Ansell 2025-09-19 8:06 p.m.
Not currently planned as it is quite expensive in very low volume.
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So around 750um then ?
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tnt
@Andrew Wingate Also see https://discord.com/channels/1361349522684510449/1418540236148838461 thread which has the pad frame and how it should be bonded out.
Tim 'mithro' Ansell 2025-09-19 8:07 p.m.
I don't think people can access that thread?
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Tim 'mithro' Ansell
I don't think people can access that thread?
Andrew Wingate 2025-09-19 8:07 p.m.
I can see it
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Tim 'mithro' Ansell 2025-09-19 8:08 p.m.
Maybe just my phone being weird?
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@Tim 'mithro' Ansell why not ? It's in #general in this discord.
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Tim 'mithro' Ansell 2025-09-19 8:09 p.m.
@Tholin - I would definitely like to have some DIP style templates. I believe @ReJ aka Renaldas Zioma needs that for the z80?
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tnt
@Tim 'mithro' Ansell why not ? It's in #general in this discord.
Tim 'mithro' Ansell 2025-09-19 8:10 p.m.
Just seems to be some weirdness of the phone client, working now. Sorry.
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The current COB footprint is too large to fit a DIP footprint
8:11 p.m.
I’ll need to make a new one
8:11 p.m.
But as it stands, I can’t even test the current one
8:11 p.m.
Still do not own a wire bonder and won’t for a few more months
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But, theoretically, should be possible. After all, the dies are of the right dimension to fit inside one of those ceramic DIP carriers.
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@Tim 'mithro' Ansell So you want one pad frame but different breakout options ?
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Tholin
I’ll need to make a new one
Andrew Wingate 2025-09-19 8:31 p.m.
Just for reference, this is what it looks like currently.
8:31 p.m.
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That's definitely not bondable. Wires can't be at more than 45 deg.
8:32 p.m.
Ah wait, nm, that footprint is not the die itself, forget it.
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Andrew Wingate 2025-09-19 8:33 p.m.
I was more making a visual model than anything concrete, just trying to engage some conversation and see if there are opinions so I may gather a consensus of sorts.
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Okay, I don’t think it needs to be scaled down much to fit routing to the pins
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Tim 'mithro' Ansell 2025-09-19 8:45 p.m.
@tnt - I think there are missing traces from the bond pads to the edge pads?
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Andrew Wingate 2025-09-19 8:46 p.m.
correct, there are no traces on anything
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tnt
@Tim 'mithro' Ansell So you want one pad frame but different breakout options ?
Tim 'mithro' Ansell 2025-09-19 8:47 p.m.
Eventually, multiple standard templates for everything and it being someone else's problem 😛
8:48 p.m.
But in the short term, one or two pad frames and one or two breakouts.
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For reference, this is what it looks like inside an actual DIP-40 ceramic carrier. https://www.spectrum-semi.com/sites/default/files/pdfs/CSB04079.pdf
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Relevant section. I believe I can design a COB footprint based on these dimensions. I also have diagrams for DIP-48 and DIP-64 carriers to reference if more pads are needed. (edited)
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Well, that works!
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Tim 'mithro' Ansell 2025-09-23 12:28 a.m.
@Tholin - Cool! What size is that?
12:29 a.m.
@Tholin - What design rules does that end up being?
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Its JLCPCB’s two-layer PCB rules
7:38 a.m.
Its basically just a DIP-40 carrier, but on PCB
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Tim 'mithro' Ansell 2025-09-23 8:30 p.m.
@Tholin - Link to repo?
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Tim 'mithro' Ansell
@Tholin - Link to repo?
Experimenting with Chip On Board setups for GF180MCU chips, most importantly gf180 Caravel. - AvalonSemiconductors/gf180mcu_cob
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Tim 'mithro' Ansell 2025-09-23 8:37 p.m.
Awesome, thanks!
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Tim 'mithro' Ansell 2025-09-23 10:30 p.m.
I wonder if you could "drop" the chip in a cut out to make the whole thing flatter, bond wires shorter.....
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algofoogle (Anton Maurovic) 2025-09-24 1:22 a.m.
4-layer PCB, and a die-shaped hole milled out of the top substrate, you mean?
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Tim 'mithro' Ansell 2025-09-24 1:55 a.m.
@algofoogle (Anton Maurovic) - yeah, something like that
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How would that work with the epad?
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Tim 'mithro' Ansell 2025-09-24 4:59 a.m.
@urish - You mean the backside silicon connection? I believe you can still have pads in the hole.
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algofoogle (Anton Maurovic) 2025-09-24 5:02 a.m.
Is the back of the die electrically connected, though? I don’t think it was in the Efabless runs (or at least not intentionally); @Tim Edwards ?
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Leo Moser (mole99) 2025-09-24 5:03 a.m.
No, it should be not. The epad refers to QFN packaging and is also wire bonded.
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algofoogle (Anton Maurovic) 2025-09-24 5:05 a.m.
Btw, I think the hole I was talking about is called a “PCB Cavity”, and there are different ways to do it and different options supported. https://www.pcbway.com/blog/PCB_Basic_Information/What_is_Cavity_PCB_0882350d.html Related: die embedding https://www.pcbway.com/blog/Engineering_Technical/Use_Embedded_Components_To_Improve_PCB_Performance_And_Reduce_Size.html
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Tim 'mithro' Ansell 2025-09-24 5:33 a.m.
Yeah PCB Cavity is proper name.
5:36 a.m.
They have an picture on that last page like this
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oooh that's interesting re: image sensors, since it'd provide some protection to the bond wires without encapsulation
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Tim 'mithro' Ansell 2025-09-25 7:40 p.m.
BTW - People here might be interested in the discussions in #die-sorter as well.
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BreakingTaps
oooh that's interesting re: image sensors, since it'd provide some protection to the bond wires without encapsulation
(sorry, I was just directed here by someone chatting about garage phabs and just wanted to say I'm a fan of your videos! I'll go back to being a normal person now)
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BreakingTaps started a thread. 2025-09-26 5:15 p.m.
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